In recent years, substantial efforts have been made toward improving the electrical characteristics, reliability and high frequency performance of certain types of field-effect transistors (FETs) and particularly Schottky-gate, GaAs field-effect transistors. These Schottky-gate, GaAs FETs have recently been used to replace the more expensive parametric amplifiers and travelling wave tubes and also some analagous silicon devices, and these new FETs have demonstrated an improved electrical performance, longer operating life, and greater design flexibility relative to these earlier devices. For example, a TWT tube lasts approximately 1,000 hours, whereas GaAs FETs have been rated at more than 20,000 hours lifetime.
Additionally, many technical articles have appeared in recent months describing various types and features of the latest, state of the art GaAs FETs. Typical of these technical articles is a recent publication by Stacey V. Bearse in Microwaves, February 1976 entitled "GaAs FETs: Device Designers Solving Reliability Problems", at page 32. This rather extensive article, as well as the many reference articles noted on page 52 thereof, are incorporated fully herein by reference. Some of these latest state of the art GaAs FETs have been constructed using selected ion implantation doping techniques as evidenced by the GaAs FETs described in U.S. Pat. Nos. 3,914,784 and 3,912,546, issued to R. G. Hunspurger and both assigned to the present assignee. Thus, as is apparent from this prior work, the desirability for further improving the reliability, electrical characteristics and overall operational performance of these high frequency field-effect transistors is manifest.
FIGS. 1 and 2 of the drawings illustrate two specific prior approaches to GaAs FET device fabrication, and these two approaches will be discussed in more detail below with specific reference to these prior art figures. However, from a mere inspection of these prior devices shown in FIGS. 1 and 2, it will be observed that the device of FIG. 1 is an electrically unpassivated device, whereas the passivated structure of FIG. 2 exhibits an obvious undesirable drain-to-gate overlap capacitance which inherently limits the high frequency performance of this device. Another operational disadvantage of the devices shown in FIGS. 1 and 2 is the current crowding at the drain and source because of the metal contact geometry at the FET channel region.